爱魔域

由于与铝互连相比，魔域sf怎么开铜互连具有更高的电阻率和可靠性[1]，因此在微电子行业中得到了广泛的认可。最初，SiO2 被用作层间电介质（图 1）。然而，为了降低互连电容，在 90 nm 节点处引入了 C 掺杂的 SiO2 或 SiCOH [2,3]。桥接 Si-O 键被非桥接 Si-CH3 键取代，导致较低的密度，因此较低的介电常数。不幸的是，电介质的弹性模量也降低了，使加工更加困难。无孔 SiCOH 的介电常数范围为 2.7 至 3.0。通过增加孔隙率，可以将 SiCOH 的介电常数进一步降低至 2.4 或更低（图 1）。然而，弹性模量进一步降低，使加工更具挑战性。Cu 互连与多孔低 k 电介质的集成存在许多挑战，包括图案化、衬垫覆盖、化学机械抛光 (CMP) 和封装。图案化低 k 电介质最困难的挑战之一是最大限度地减少反应离子蚀刻和抗蚀剂剥离工艺造成的损坏。抗蚀剂剥离过程尤其具有破坏性，因为抗蚀剂剥离过程中的离子和自由基会从 SiCOH 表面去除甲基（图 2）[4]。表面变得亲水，材料的介电常数增加。必须优化许多工艺以最大限度地减少光刻胶剥离造成的损坏，包括碳化硅中的 C 含量和键合 [5]、光刻胶剥离化学成分 [6] 以及使用甲硅烷基化修复损伤 [4]。金属化和 CMP 处理取决于低 k 电介质中的孔径分布。出于多种原因，必须具有小（< 2 nm 直径）隔离孔 [2,7,8,9]。在金属化之前的湿法清洁步骤和 CMP [7,8] 期间，隔离的孔是可取的，以防止水和其他污染物扩散到电介质步骤中。如果孔隙连通性太高（图 3），水可能会被电介质吸收，从而导致更高的介电常数和/或降低电介质击穿的可靠性 [7,8]。一种减少 CMP 过程中吸水率的方法是使用双层多孔 SiCOH 薄膜，近表面区域（暴露于 CMP）的孔隙率低于薄膜的主体 [8]。沉积薄，随着孔径的增加，连续的金属阻挡层（例如 TaN/Ta）变得更加困难；不完全的势垒覆盖会导致铜扩散到电介质中 [9]。22 nm 节点的势垒层厚度目标约为 3 nm。因此，即使对于设计良好的多孔低 k 材料（即具有直径小于 2 nm 的孤立孔），金属厚度也接近孔径。为确保可靠性，可能需要在金属化之前使用等离子处理或保形介电沉积来密封孔隙 [9,10]。使用额外衬垫的缺点是 RC 延迟会增加 [10]。低 k 电介质的封装也更加困难，特别是对于多孔电介质，因为这些材料的模量低于 SiO2 [11, 12]。由于管芯和封装材料之间的热膨胀系数 (CTE) 不匹配，封装期间管芯中会出现应力。对于引线键合封装，由于与引线键合工艺相关的力，可能会在键合焊盘下方发生损坏，而由于环氧树脂涂层会在芯片角处发生损坏。必须通过使用 SiO2 作为最后布线层的电介质，并通过使用通孔来加强结构 [11]，来保护焊盘下方的低 k 电介质。对于倒装芯片封装，应力发生在焊料凸块下方（通常在芯片连接期间），这可能会导致低 k 电介质出现裂纹。由于与 Pb 基焊料相比，无铅焊料的高模量和更高的熔点，无铅焊料的问题变得更加困难 [12]。

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Process Challenges for Integration of Copper Interconnects with Low-k Dielectrics

Copper interconnects have gained wide acceptance in the microelectronics industry due to improved resistivity and reliability compared to Al interconnects [1]. Initially SiO2 was used as the interlevel dielectric (Fig. 1). However, to reduce interconnect capacitance, C-doped SiO2 or SiCOH was introduced at the 90 nm node [2,3]. Bridging Si-O bonds are replaced by non-bridging Si-CH3 bonds, resulting in a lower density and hence a lower dielectric constant. Unfortunately, the elastic modululs of the dielectric is also reduced, making processing more difficult. Non-porous SiCOH has a dielectric constant ranging from 2.7 to 3.0. The dielectric constant of SiCOH can be further reduced, to 2.4 or less, by adding porosity (Fig. 1). However, the elastic modulus is reduced even further, making processing even more challenging. There are many challenges with the integration of Cu interconnects with porous low-k dielectrics, including patterning, liner coverage, chemical mechanical polishing (CMP), and packaging. One of the most difficult challenges of patterning the low-k dielectric is to minimize damage from the reactive ion etch and resist strip processes. The resist strip processes are especially damaging, because ions and radicals in the resist strip process remove methyl groups from the surface of the SiCOH (Fig. 2) [4]. The surface becomes hydrophilic, and the dielectric constant of the material increases. A number of processes must be optimized to minimize the damage from resist strip, including the C content and bonding in the SiCOH [5], the resist strip chemistry [6], and use of silylation to repair damage [4]. The metallization and CMP processing are dependent on the pore size distribution in the low-k dielectric. It is essential to have small (< 2 nm diameter) isolated pores for a number of reasons [2,7,8,9]. Isolated pores are desirable to prevent water and other contaminants from diffusing into the dielectric step during wet clean steps prior to metallization and during CMP [7,8]. If pores connectivity is too high (Fig. 3), water may be absorbed in the dielectric, resulting in higher dielectric constant and /or degraded reliability for dielectric breakdown [7,8]. One approach to minimizing water absorption during CMP is to use a bilayer porous SiCOH film, with the near surrfac region (that is exposed to CMP) having a lower porosity than the bulk of the film [8]. Deposition of thin, continuous metal barrier layers (such as TaN/Ta) is more difficult as pore size increases; incomplete barrier coverage can result in Cu diffusion into the dielectric [9]. The target for barrier layer thickness at the 22 nm node is ~ 3nm. Hence, even for well designed porous low-k materials (i.e., with isolated pores less than 2 nm in diameter) the metal thickness is approaching the pore size. To ensure reliability, it may be necessary to seal the pores prior to metallization, using plasma treatments or conformal dielectric deposition [9,10]. The drawback to using additional liners is that the RC delay will be increased [10]. Packaging is also more difficult with low-k dielectrics, especially for porous dielectrics, due to the lower modulus of these materials compared to SiO2 [11, 12]. Stress occurs in the die during packaging due to the mismatch in coefficient of thermal expansion (CTE) between the die and the package materials. For wirebond packages, damage can occur under the bond pad, due to force associated with the wirebond process, and at the chip corners, due to the epoxy coating. The low-k dielectric under the bond pads must be protected, by using SiO2 as the dielectric for the last wiring layers, and by using vias to strengthen the structure [11]. For flip chip packages, the stress occurs underneath the solder bumps, (typically during chip joining) that can cause cracks in the low-k dielectrics. The problem becomes even more difficult with Pb-free solder, due to the high modulus and higher melting point of Pb-free solder compared to Pbbased solder [12]. A number of processes must be optimized to ensure high yield and reliability, including the bond pad layout, the solder composition, the solder reflow process, and the adhesion of the dielectrics and barrier layers in the low-k stack [13].